[egenix-users] SIGBUS from mx/BeeBase/mxBeeBase/btr.c on HP-UX, Alpha, IRIX, Solaris

[M.-A. Lemburg]

Albert Chin wrote:
> On Wed, Jan 11, 2006 at 10:20:19AM -0600, Albert Chin wrote:
>> On Wed, Jan 11, 2006 at 05:00:25PM +0100, M.-A. Lemburg wrote:
>>> Are you compiling this on a 64-bit machine ?
>> They are all 64-bit CPUs but we are building 32-bit objects.
>>
>>> FWIW: When trying the test.py script on an AMD64 machine it
>>> runs through fine.
>> Yeah, we tried on RHEL 3/AMD64 and 4/AMD64 with success.
>>
>>> It's been ages since I last looked at the code, so it's hard
>>> to tell what the problem could be.
>> What I don't understand is why this doesn't work:
>>   *mkey1 = 0;
>>   *(mkey1 + 1) = 0;
>>   *(mkey1 + 2) = 0;
>>   *(mkey1 + 3) = 1;
>>   val = *mkey2;
>>   ^^^^^^^^^^^^^ SIGBUS
> 
> I think it's a memory-alignment issue. Maybe unsigned longs on the
> problematic platforms need to be aligned to an even address, or
> something like that. If so, how to fix?

The above does hint at that yes.

Where exactly in test.py do you get the bus error ?

It's possible that on your platforms, a keysize of 10 (which
is used in test.py) is not allowed. Perhaps you could try 16
instead.

-- 
Marc-Andre Lemburg
eGenix.com

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